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INDEX PRELIMINARY
MX98705
100 BASE-TX PHY-PMD TRANSCEIVER
1. FEATURES
* Complies with IEEE 802.3 Standards * Integral 10 Mb/s Buffer for Dual 10 Mb/s&100 Mb/s Applications * Baseline Wander correction * Adapative Equalization * 25 MHz to 125 MHz Transmit Clock Multiplier * Five Bit TTL Nibble at 25 MHz Input/Output * 25 MHz received recovery clock * Operates over 100 Meters of STP and Category 5 UTP Cable (>7.5 dB) * Single +5V Supply * 52 PQFP package
2. GENERAL DISCRIPTION
The MX98705 is a fully intergrated physical layer device supporting 100Base-TX or FDDI over copper applications. The MX98705 integrates 125 MHz clock recovery/generation, receive adaptive equalization, and baseline wander correction, it provides 5-bit parallel interface to any MAC controller. The MX98705 receive section includes an adaptive equalizer with DC baseline wander compensation, MLT-3 to NRZ decoder, and a 125 MHz receive clock recovery circuit. The transmit section provide NRZ to MLT-3 for 100Base-TX and a buffer for 10 Mb/s application.
3. BLOCK DIAGRAM
4. PIN CONFIGURATION
TDAT4 TDAT3 TDAT2 TDAT1 TDAT0 CLKIN VDD TXCLK RDA0 RDA1 RDA2 RDA3 RDA4
Clock recovery
TDAT0-4 TXPLL (NRZ to NRZI) RXPLL (NRZI to NRZ) RDA0-4 SDO N10/100 ILBEN
Signal detect
NRZI to MLT3
100M
TXOP/N
DRIVER
PXIP/N EQ Voltage reference
Baseline wander correction & MLT3 to NRZI 10TIP/N
EQ
10M
GND NC NC RSCLK SDO VDD NC NC GND NC NC VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13
40 41 42 43 44 45 46 47 48 49 50 51 52
MX98705
39 38 37 36 35 34 33 32 31 30 29 28 27
GND NC NC N10/100 LBEN VDD TXOE VDD RFA RFB GND GND GND
26 25 24 23 22 21 20 19 18 17 16 15 14
VDD REF GND TXOP TXON VDD 10TIP 10TIN EQS VDD RIN RIP GND
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5. PIN DESCRIPTION
PIN 1 2, 3 4 5 6 7, 8 9 10 11 12 13 14 15, 16 17 18 19, 20 21 22, 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37, 38 39 40-44 45 46 47 48-52 PIN NAME GND NC RSCLK SDO VDD NC GND NC NC VDD VDD GND RIP RIN EQS 10TIN 10TIP VDD TXON TXOP TXREF VDD GND GND GND RFB RFA VDD TXOE VDD LBEN N10/100 NC GND TDAT4-0 CLKIN VDD TCLK RDA0-4 TYPE O TTLO TTLO O I O I I I O I I I TTLI TTLI O TTLI TTLI TTLO TTLO DESCRIPTION Ground for PADs No connection 25MHZ recovered receive clock Signal detect output. Being high after RXH/RXL inputs is available (>40ms) VDD for PLL digital circuits No connection Ground for receive PLL No connection No connection VDD for receive PLL VDD for EQ circuit Ground for EQ circuit Differential receive signal input form magnetics VDD for EQ circuit 3 level mode select for equaliser, high=min, open=auto, low=full Differential 10 base T input. This signal is output on the TXON & TXOP when N10/100 is held low VDD for output line Driver Differential line driver outputs to drive magnetics Ground for output line Driver Line driver current reference set-up pin. By connecting 500 resistor to GND is recommended. VDD for PHY bias circuit Ground for chip substrate GND connectionn Ground for EQ circuit Ground for Transmit PLL Internal Ground reference. NC or Connect to GND Internal feedback reference current generation point. By connecting 1.4K resistor to GND or RFB VDD for Transimit PLL Output Enable. Tri -state TX drivers when TXOE is low. VDD for PHY WELL contact Loopback enable input. High is loopback mode, low is normal mode 10/100M driver selection. High is 100M, low is 10M driver No connection Ground for PADs Parallel input to transmit channel 25 MHz reference clock to PLLs VDD for PADs 25 MHz transmit reference clock from transmit PLL 5-bit parallel received data
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6. FUNCTIONAL DESCRIPTION
The functional blocks of the device are shown in Fig.1 These are described below: 6.1 Transmit Section 6.1.1 Transmit 125 MHz Phase Lock Loop (PLL) This circuit consist of a VCO with 125MHz central frequency and built-in loop filter. The 125 Mhz is divided by 5 to generate a 25 Mhz output clock which is phase compared with a 25 MHz crystal reference clock which is an input through pin CLKIN. This 25 MHz clock is then sent to the PCS layer to pace in the 5 bit nibble data. Due to built-in filter, no extra filter components are needed which simply the system design. 6.1.2 Five Bit Nibble or 125 MHz Shifter Data is input to the transmit side in 5-bit form on pins TDAT0-4. This NRZ data is clocked in on the posotive edge of the 25 MHz clock through TXCLK pin. The parallel data is first loaded into a 5 bit wide register prior to being loaded into a 5 bit PISO where it is converted into a serial data stream. The last stage of the shifter is a converter to change the data from NRZ to NRZI. 6.1.3 NRZI to MLT3 Encoder The serial data from the shifter then passes through an encoder which converts the NRZI binary data into the three level MLT-3 format for transmission by the "TXO" outputs. 6.1.4 Transmit Line Driver Both of the 10Mb/s and 100Mb/s line driver share the same output pins TXOP and TXON. The N10/100 pin is used to control which driver is active and allowed to driver the line. When N10/100 is held high the MLT-3 data is output by the 100Mb/s driver. This driver is designed to drive a nominal output impedance of 50. Output current is set by the value of an external resistor (Rext) from pin "REF" to GND. Final output current at the "TXO" output is a multiple of this current and is defined as: ITXO(mA)=23/REXT(k) Transition times of the "TXO" outputs are matched and internally limited to approx. 3.0ns to reduce EMI emissions. When N10/100 is held low, the 10Mb/s driver is selected. This 10Mb/s driver consists of a differential analog buffer designed to take a fully cable conditioned 10Mb/s signal from the filter output of existing 10BaseT electronics. The 10BaseT signal is input on pins 10TIP/N. The output current of the buffer is determined by the same external REXT as 100Mb/s driver. The unselected driver is switched to a tristated mode for saving power. In additional, when TXOE pin is held low, both 10Mb/s and 100Mb/s drivers are tri-stated regardless of the mode selected by N10/100 pin. When operating in single 100Mb/s applications a 1:1 turn ratio magnetics is recommand, therefore, to attain the desired line driving current of 40mA out of the secondary a TXO output driver of 40mA is required. Using the above formula it will be found that 560 is the nearest prefered value to that required to give the 40mA. 6.2 Receiver Section 6.2.1 Equalizer The equalizer circuit is necessary to compensate for signal degradation due to cable lossers, however over-equalization must be avoided to present excessive overshoots resulting in errors during the reception of MLT-3 data. Three operating modes are therefore provided. These three operating modes are controlled by the state of tristate input "EQS" and are described below: 1)Auto Equalization ("EQS" floating) Fully automatics equalization is achieved through the use of a feedback loop driven by a control signal derived from the signal amplitude. This provides adaptive control and prevents over-modulation of the signal when short cable lengths are used. 2)Full Equalization ("EQS" low) In the mode, full equalization is applied to the input signal irrespective of amplitude. 3)No equalization ("EQS" high) The equalization circuit is disabled completely during this mode. 6.2.2 Baseline wander correction Any DC offset existing on the received signals will be corrected by this feed forward baseline tracking circuit.
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6.2.3 Signal Detector A signal detect circuit is provided. The circuit continuously monitors the amplitude of the input signal being received on pins RXIP/N. While the input signal reaches the specified level (>0.6VP.P), the equalization circuits start to pre-process, then the SDO is asserted high after 80ms (max.) pre-process time. Conversely if the signal level falls below a threshold, then SDO will go low. 6.2.4 Receive PLL Clock Recovery This block generates 125 MHz recovered clock that is locked to the incoming data stream which is feed from MLT-3 to NRZI converter. The PLL is first centered to the transmit clock multiplier, once a valid input signal is present, the PLL will lock to the incoming data stream. 6.2.5 125 MHz shifter to Parallel Data The data stream is clocked into the serial to parallel register using the 125 MHz clock. This data is latch prior to being clocked out on pins RDAT0-4. A 25 MHz clock, derived from the 125 MHz PLL clock divided by 5, is used to clock the parallel data and is output to pin RSCLK. 6.2.6 Loopback Logic A low level on ` L B E N ' pin defines normal operation, a high level defines loopback mode. In loopback mode, the transmit data is internally routed to the receive circuitry, SDO is forced to be high on level and the TXOP/N outputs are disabled.
8. RECOMMENDED OPERATION CONDITIONS
Vcc Supply Voltage Operating temperature Rext REF 5V to 5% 0C to 70C 560 1% 1.4K 1%
7. ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Vcc Supply Voltage Range ......... -0.3V to 6V Storage Temperatur .................... -65C to 150C Input Voltage Range Lead Temperature (10 sec) ......... 60C Digital Inputs ............................... -0.3V to Vcc ESD ............................................ 2k VHHBM Output Current TXOP, TXON .............................. 70mA All other outputs .......................... 10mA
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9. ELECTRICAL CHARACTERISTICS
Characteristics Power supply current TTL input high voltage TTL input low voltage EQS input high voltage EQS input low voltage EQS floating voltage EQS input high current EQS input low current TTl output high voltage TTL output low voltaage TXOP/N output current Differential RXIP/N signal voltage Symbol IDD VIH vIL VIH VIL VIZ VIH VIL VOH VOL Min. 2 4.2 0.8 VDD/2 500 -500 2.4 0.4 40 70 1.4 Value Typ. 95 Max. 0.8 Units mA V V V V V uA uA V V mA VP-P Conditions device only
VEQS=VDD VEQS=0V IOH=4mA IOL=4mA Rext=500, 100Mb/s 10Mb/s measured on device pins 100 Mb/s data, 0m Cable RXIP/N floating
RXIP/N common mode voltage RXIP/N impedance Signal detect threshold
VCOM ZIN VTH
3.3 10 0.6
V KW Vpp
10. AC CHARACTERISTICS
Characteristics Wareform TXOP/N rise/fall times RSCLK frequency RSCLK tolerence RSCLK M/S tatio RSCLK to CLKIN propagation delay (1) TDAT0-4 to TXCLK setup time TDAT0-4 TXCLK hold time RDAT0-4 valid to RSCLK RSCLK to RDAT0-4 invalid RSCLK M/S ratio TDAT0-4 to CLKIN setup time RXIP valid to SDT time delay (2) (3) (4) (5) (6) (7) Min. Value Typ. 2.5 25 100 4.5 10 0 15 15 40/60 5 80 Max. Units ns MHz ppm % ns ns ns ns ns ns ns ms Conditions 50W load
40/60
60/40
Transimit PLL is lock
40/60
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11. WAVEFORM TIMING
(1) CLKIN (6) TXCLK (2) (3) TDAT 0-4 Valid data Valid data
TXCLK (4) (5) RDAT 0-4 Valid data Valid data
RXIP/N
Input level over threshold (7)
SDT
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12. APPLICATION NOTE
GND
VDD
GND
VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13
39 38 37 36 35 34 Transmit 33 GND 32 Plane 31 Receive GND Plane 30 29 Line Drive 28 GND Plane 27
Digital GND Plane
VDD 40 41 42 43 44 45 46 47 48 49 50 51 52
GND
VDD VDD
GND GND GND
Chassis GND Plane
26 25 24 23 22 21 20 19 18 17 16 15 14 GND
LAYOUT GUIDE
VDD 10TIP 10TIN EQS VDD
VDD REF GND
Magnetic Module
RJ-45
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12.1 LAYOUT GUIDE
System VDD Plane VDD (Pin 46) 22u 0.22u GND (Pin 1, Pin 39) FB 0.01u 0.1u
GND (Pin 29)
VDD (Pin 34) VDD (Pin 32) 0.1u
VDD (Pin 12) FB 0.01u VDD (Pin 6) 0.1u 0.1u
VDD (Pin 13)
VDD (Pin 17)
VDD (Pin 26)
0.1u
0.1u
0.1u
GND (Pin 9, Pin 14, Pin 27, Pin 28) FB 0.01u 0.1u GND (Pin 24) System GND Plane VDD (Pin 21)
Note : The MX98705 is designed with Macronix mixed mode technology. The above layout guide is recommended for good performance. The GND plane is devided into digital ground, transmit ground, receive ground and line drive ground. Following the layout guide, the system will be with best noise emmunity. Pin1 and Pin39 are connected to digital GND plane. Pin34 is connected to Transmit GND plane. Pin9, Pin14, Pin27 and Pin28 are connected to Receive GND plane. Pin24 is connected to Line Drive GND plane.
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13. PACKAGE INFORMATION
52--Pin Plastic Quad Flat Pack
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MACRONIX INTERNATIONAL CO., LTD.
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TEL:+886-3-578-8888 FAX:+886-3-578-8887
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
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